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Computer M-3



A universal of small size digital computer M-3 according to its exploitation characteristics was to be used in scientific researching institutes and design bureau. The tasks that were solved by the computer M-3 were integrating of usual differential equations and equations in derivatives (as linear as nonlinear), solving of linear equation systems with some unknown algebraically and transcendental equations and others.

The scientific adviser of the project is I.S. Brook, a correspondent member of AS USSR.

The technical project was developed initiatively in 1953 by collaborators of electro system laboratory of Energy Institute. The laboratory was reorganized into the laboratory of directing machines and systems in 1956.

The main developers of the technical project are: N.Y. Matukhin (the head), V.V. Belinskij, U.B. Przhiemskij, N.A. Dorokhova, A.B.Zalkind, G.I. Tanetov, A.N. Patrikejev, A.P. Morosov.

There was not any official task for the M-3 creation and the problem about its production also wasnt solved. But three members of the academy were interested in the computer. They were: A.G. Iosifyan, V.A. Amburzimyan and S.P. Korolev. They made an agreement with I.S.Brook about the joint finishing works and three computer sample production.

Developers from AS and collaborators of other organizations that were interested in it finished the project and made design papers for the computer production. V.M. Dolkart, V.M. Kagan, T.P. Lopato, V.N. Ovcharenko, B.B. Melik-Shakhnazarov, A.P.Tolmasov, V.A. Morozov, I.A. Skripkin, A.V. Pipinov, V.N. Semenova jointed the project. B.M. Kagan was the organizer of design and technological papers making, producing preparations, software developing and state experiment preparations.

Three computers M-3 were finished and debugged in 1956. The first one was for state experiments, the second one was sent to Erevan Mathematical Institute of Armenia Academy of Sciences and the last one was got by S.P. Korolevs organization.

By this time necessary software had been developed. So at state experiment computer M-3 was with worked software. The experiment was successfully finished in 1956.According to the results computer M-3 was recommended for the serial production. But computer producing plats didnt plan its production. At this time building of Minsk plant of computer technology was going to be finished but it didnt have any orders. Then there was a decision about the producing of computer M-3 at this plant. So since 1958 the computer M-3 producing began at Minsk plant that was for some years. Then the design papers were renamed and the computer got the name Minsk.

According to the design papers of computer M-3 with technical help of Armenia specialists computer Razdan was created, the first computer was in 1956 in Erevan Institute of Mathematical Computer Building. So computer M-3 creation played an important role in projecting and producing of computers in Byelorussia and Armenia. A significant contribution of computer M-3 was made by G.P.Lopat (in Minsk plant) and G.G. Melik-Pashaev (in Erevan Institute of Mathematical Computer Building).


The main technical characteristics


System of number presenting with fixed point


Quantity of binary classes 30, except sign class

that meets with 9 classes of decimal numbers


Arithmetics unit of parallel type


Memory on the magnet drum with parallel choice of 2048 number volume


Average speed of work 30 operations pre second


Code system two-address


Data input speed 30 numbers per minute with transmitter T-50, 1200 numbers per minute with photoelectron transmitter


Information output speed 30 numbers per minute (results are in decimal system or octuple system)


The volume of memory can be raised up to 4096 numbers by connecting with the second memory box.

There is an opportunity to connect with a machine of separate box of high speed memory that provides the working speed rise at average up to 1500-2000 operations per second.


The main units of the computer


There are four main units in computer M-3: arithmetical unit AU, program sensor PS, memory device M and input, output device.


Arithmetical unit AU of computer M-3 of parallel type. This allows getting higher speeds of arithmetical operations fulfillment. The time of main arithmetical operations fulfillment in AU of computer M-3 is: adding - 60 microseconds, subtraction 75-120 ms, multiplying 1900 ms, dividing 200 ms.

Arithmetical unit consists of four trigger registers A, B, C and D. D register has functions of parallel 30-class summarizer and transfer units before summing. According to its functions its very different from other registers. There is a unit transferring before summing and per class summing. C register is a connector with other units of a computer. Through C register information is transferred into memory device when inputting, program instruction codes are transferred from memory device into PS, there is a code transferring from one cell of MD into another cell and also information input from MD to printing devices.

Before arithmetical operations numbers in registers are in the following positions: in register A addendum, subtrahend, multiplicand, dividend, in register B addendum, subtrahend, dividend, in register C multiplicand. Initial numbers, when logical multiplying, are placed in registers A and C.

At the end of an operation sum, product are formed in register B and transferred to register C. And result at logical multiplying are formed in register C and transferred to register B. In all cases at the end of operations the results are in registers B and C simultaneously and kept till next receiving in them. This gives an opportunity to use a result that is kept in register B in further operations.

The device of register allows doing the following simple operations:

- parallel information receiving from register C

- taking inverse code of storing information in register

- installation of all triggers at 0 of register

In the register B you can do:

- installation of all triggers at 0 of register

- taking reverse code

- parallel receiving from register C

- parallel transferring to register C

- shifting of content to the right/left


In the register C you can do

- installation of all triggers at 0 of register

- parallel receiving from memory device

- parallel receiving from register B

- parallel transferring to registers A and B, SR and program sensor, logical input of their UVV and logical parallel output from AU into UVV

- shifting of content to the right/left

- forming logical multiplication result

- typing of information into the register


Program sensor is automatically controlled with computer units AU, MD, UVV. While solving problem program sensor according to the program takes numbers from MD and places them in registers AU fulfilling necessary operations, sends the result to necessary cell of MD and prints it, if the instruction is given. In the process of fulfillment of this cycle that corresponds to the fulfillment of one program instruction, instruction address is identified that must be done in the cycle.All these steps that correspond to one instruction program sensor fulfills in the following logic during 8-cycle and the content of cycle changes depending on instruction.

Program sensor consists of blocks: local program sensor LPD, operation block OB, impulse distributor ID, selective register SR, starting register SR.

Block LPD is for arithmetical unit controlling when it fulfills the following: adding, subtracting, multiplying, dividing, input and output in groups of 3 or 4 classes, logical multiplication. There are also three sign triggers of A, B, C, registers.

Operation block is keeping and decoding an operation code of a program instruction that is fulfilled with the computer. The operation code is placed in 1-6 classes of C register. These classes are connected with 1-6 triggers of operation block register. According to the code system operation block gives to LPD blocks and input/output block commands to fulfill an operation according to the instruction. Besides, the block gives to MD a command record if instruction foresaw operation result printing. Otherwise at the end of operation block sends a command starting to block ID that provides the next cycle of work.

Impulse distributing block

Computer M-3 doesnt work simultaneously, i.e. there are united cycle impulses for the whole device that could distribute the speed of work. Every unit gets an impulse command, fulfills operations and sends impulse answer, denoting that the operation is fulfilled and the next operation can be started. Receiving the answer about the finishing of an operation ID block sends a command to MD of reading of the following instruction and at the same time sends from SR to SR the address of this instruction. When impulse of answer about the finishing of reading instruction comes depending on the code of operation IR sends different controlling impulses to MD, OB, SR, SR, AU and LPD. All cycle of ID consists of 8-cycle, number of passing cycles is controlled with scalar of ID. The content of cycles can change according to instruction code.

Starting and selective registers

12 classes triggers of SR and SR are to keep and readdress transforming of numbers and commands that are chosen from MD. Every trigger of SR is connected through recodes of incorrespondent with trigger of scalar marker impulses of MD. The coincidence of SR register condition and given address is fixed with a scheme in . In SR in the process of fulfillment of given instruction an address is formed of the next program instruction. Usually instructions go one by one in the order of their recording in MD that is why there a in SR. But if instruction fulfillment is of conditional or unconditional passing when the address of the next instruction is not according to the order then information comes from SR. All impulses that control SR and SR work come from ID. Except these main functions registers SR and SR allow to stop in necessary address and electron output of information.

Memory device MD As a memory device in computer M-3 a rotating ram is used that is covered with ferromagnetic layer with a system of head for recording and reading of a signal. This magnetic memory device is to keep program instructions, initial data of auxiliary numbers, intermediate and final results that are got in the process of problem solving. Memory device is of parallel type. Recording and reading are simultaneously done in 31 channels (30 number classes and 1 sign class) on the ram, the place in defined according to the ordinal number of a marker impulse. To get the logic of marker impulse on the surface of the ram 2048 impulses are recorded. Against the path where the record is there is a marker head which signals form marker impulses. Another head zero - is so placed that against it only one signal is recorded that forms zero signal. It corresponds to the time of a gap between 2048 and 1 marker impulses.

Technical data of memory device


Volume 2048 30-class binary numbers

Average time of choice 10 ms

Density of record 3.2

Number of rotations 3000 per min

Diameter of the ram 216 mm

Ferromagnetic layer alloy of nickel-cobalt, thickness- 3-5

Frequency of marker impulses 108 kHz


Input/output device

Input device: the input of information from paper perforate tape is carried out with the help of transmitter T-50. Information inputting in the computer consists of a program instruction logic, initial digital data and auxiliary numbers. Instruction codes are given in octuple system and codes of initial data and auxiliary numbers are given in decimal system. Code are placed on the tape with the help of perforator in binary code way. Except codes service signs are perforated on the tape that control input device. Input device reads information from the tape, decodes it, gives it in double system and transfers it to memory device. Input of information can be automatic and by hands. There is an opportunity to use photo reading device to input information.

Output device: output of necessary intermediate and final results is carried out on the printing device teletype that is a electronic typing machine that has additional mechanisms: distributive, decoding, perforating and relay. All these mechanisms in interaction produce a combination of electrical signals that are sent to the enter of distributive mechanism and to the mechanism of printing. With printing perforating mechanism can perforate printing signs on the tape. In computer M-3 a roll teletype is used that is provided with perforator thanks to what it is possible to get results on the perforated tape. The tape can be kept long for the next input of information into a computer. Printing controlling of results with necessary interval and a definite number of columns is carried out with the help of standard step searchers. There is an opportunity of electron output of information. Electron output is to display on the oscilloscope a diagram on witch axes of ordinate volume is put that is proportional to 5 higher classes of a given number and on the axes abscissa volume that is proportional to the number of passing outputs.

Electrical feeding of the computer M-3


The feeding device consists of electrical aggregator and box of feeding. Synchronized engine A-62, generator C-7 of higher frequency 240 v 200 GHz and generator of direct current that gives direct voltage 240 V. Feeding aggregate is placed in separate room. In the feeding box voltage 240 V and 200 GHz becomes direct voltage that is necessary for the computer feeding. There is stabilization of some voltage and distribution of voltage inboxes of the computer. There are straitens, stabilizations, controlling schemes, protection and signaling, control devices. For computer electron schemes feeding the following levels of voltage are used: +70, +120, +150, +240, +350, +450, and 170.

All voltage is given with the help of flexible cabals.


Construction of the computer M3

All computer hardware is placed into three boxes and on one mobile table in the main box 1 there is an arithmetical bundle, programming , electron controlling block of input/output and the main . In the box 2 there is a memory device, magnetic ram, amplifier, a scheme of memory device controlling. In he box 3 feeding hardware: strainers, stabilizations, systems on on/off and computer protection. On the mobile table there is a teletype, panel of input/output device, transmitter, photo input device, blocks of relay and steps searchers.



A B C D


Scheme of units and block of the computer

A- mobile table, B box 1, C box 2 , D - 3

1- arithmetical unit, 2 main , 3 operation block, 4 local program sensor, 5- electron block of input/output device, 6 selection register, 7 starting register, 8 impulse distributive block, 9 scalar of marker impulses, scheme of comparison and block of magnetic memory controlling, 10 amplifier of recording andreading, 11 magnetic ram, 12 stabilizations, 13 - , 14 straitens, 15 teletype, 16 - panel of input/output device, 17 transmitter, 18 photo input device, 19 blocks of relay and steps searchers



The units of the computer are constructed on the duralumin frames that are placed on the carcass of boxes. In the box 1 there are three frames. In the box 2 there two frames. The field of each frame is gratings on witch standard platforms are placed for sub blocks. Sub blocks have three main sizes: double lamped 90x48x120 mm, one lamped 60x48-120 mm and four lamped 208-48-120 mm. A sub block is connected with the platform with the help of (20- or14- contacted).

For lamp cooling there is ventilation. The system of ventilation separate, air is taken from lower part of the frame through grating window goes through row of lamps and is taken away with ventilators.


Area that is taken with separate units of the computer;

- box 1 (arithmetical unit and controlling device) 1.1sq m

- box 2 (memory device) 0.7 sq m

- box 3 (electron feeding) 0.9 sq m

- mobile table (input/output devices) 0.6 sq m




Tasks programming


The system of instruction coding of M-3 is double addressed. The code of instruction takes all 30 classes of numbers, except the 31st class of a sign. An instruction can have arbitrary sign. Six high classes of an instruction are for operation code, the rest 24 are for addresses, for each address 12 classes. It is easy to code instructions in the octuple system, combining every three double classes in one octuple one. So, operation code has two octuple classes, addresses four. Instructions must be perforated on the tape of a perforator and input into the computer according to octuple system. Lower there is a structure of number and instruction codes.


Double classes



Structure of number and instruction codes



Command codes of arithmetical operations and logical multiplying are formed according to the following way: the second figure of the code is a type of an operation (adding, multiplying, subtracting and so on), the first figure is a sign (is it necessary to do the recording of the result into the memory device and so on),. The taken values of the code figures are the following:


The second figure of the code the main sign


*0 adding

*1 subtracting

*2 dividing

*3 multiplying

*6 logical multiplying


The first figure of the code auxiliary sing


0 operation with numbers from the first and second addresses, the result is recorded into the memory device according to the second address

1 operation with numbers from the first and second addresses, the result is not recorded

2 - operation with numbers from the first address and with the result from the previous operation that is kept in the arithmetical bundle, the result is recorded into the memory device according to the second address

3 operation with numbers from the first address and with the result from the previous operation that is kept in the arithmetical unit, the result is not recorded

4 operation with numbers from the first and second addresses, the result is recorded into the memory device according to the second address and printed

5 operation with numbers from the first and second addresses, the result is not recorded, but the operations are with number modules

6 operation with numbers from the first address and with the result from the previous operation that is kept in the arithmetical unit, the result is recorded into the memory device according to the second address and printed

7 operation with numbers from the first address and with the result from the previous operation that is kept in the arithmetical unit, the result is not recorded, but the operations are with number modules



Command code of computer M-3





code
The action
00
+
the content of the second address is added to the content of the first address and the result is recorded according to the second one
10
+..
the content of the second address is added to the content of the first address and the result is not recorded
20
+
The content of the first address is added to the result of the previous action and the result is recorded according to the second address
30
+.
. The content of the first address is added to the result of the previous action and the result isnt recorded
40
+
.the content of the second address is added to the content of the first address, the result is recorded according to the second one and recorded
50
i + l,
.module of the content of the first address is added to the module of the content of the second address and isnt recorded
60
+
. the content of the first address is added to the result of the previous action
the result is recorded according to the second address
70
/+/
The module of the first address content is added to the module of the result of the pervious action but isnt recorded
01
-
. the content of the first address is subtracted from the content of the second address and the result is recorded according to the second address
11
-,
. the content of the first address is subtracted from the content of the second address but the result isnt recorded
21
-
. the content of the first address is subtracted from the result of the previous action and the result is recorded according to the second address
31
-,
the content of the first address is subtracted from the result of the previous action and the result isnt recorded
41
-
the content of the first address is subtracted from the content of the second address and the result is recorded according to the second one
51
/-/,
The module of the first address content is subtracted from the module of the second address content, the result isnt recorded
61
-
. the content of the first address is subtracted from the result of the previous action and the result is recorded according to the second address and printed
71
/-/
The module of the first address content is subtracted from the module of the second address content, the result isnt recorded
02
:
The content of the second address is divided into the content of the first address, the result is recorded according to the second address
12
: ,
. The content of the second address is divided into the content of the first address, the result isnt recorded
22
:
.The result of the previous action is divided into the content of the first address and the result is recorded according to the second address
32
: ,
The result of the previous action is divided into the content of the first address and the result isnt recorded
42
:
The result of the previous action is divided into the content of the first address and the result is recorded according to the second address and printed
52
/ : /,
Module of the second address content is divided into the module of the first address content, the result isnt recorded
62
:
The result of the previous action is divided into the content of the first address and the result is recorded according to the second address and printed
72
/ : /
Module of the result of the previous action is divided into the module of the first address content, the result is not recorded
03
. the content of the fist address is multiplied by the content of the second address, the result is recorded according to the second address
13
,
the content of the fist address is multiplied by the content of the second address, the result isnt recorded
23
.the result of the previous action is multiplied by the content of the first address, the result is recorded according to the second address
33
,
.the result of the previous action is multiplied by the content of the first address, the result isnt recorded
43
The content of the second address is multiplied by the content of the second address, the result is recorded according to the second address and printed
53
/ /,
Module of the second address content is multiplied by the module of the first address content, the result isnt recorded
63
the result of the previous action is multiplied by the content of the first address, the result is recorded according to the second address and printed
73
//,
.module of the result of the previous action is multiplied by the module of the first address content, the result isnt recorded
06
/\
the content of the second address is logically multiplied by the content of the first address, the result is recorded according to the second address
16
/\ ,
the content of the second address is logically multiplied by the content of the first address
26
/\
The result of the previous action is logically multiplied by the content of the first address, the result is recorded according to the second address
36
/\ ,
. The result of the previous action is logically multiplied by the content of the first address, the result isnt recorded
46
/\
. the content of the second address is logically multiplied by the content of the first address, the result is recorded according to the second address and printed
56
/ /\ /,
. Module of the second address content is logically multiplied by the module of the first address content, the result isnt recorded
66
/\
The result of the previous action is logically multiplied by the content of the first address, the result is recorded according to the second address and printed
76
/ /\ /,
. module of the result of the previous action is logically multiplied by the module of the first address content, the result isnt recorded
07 ; 27
Number input, a number from perforated tape is recorded according to the second address, it isnt kept in the register
05 ; 15
The content of the first address is transferred to the second register and saved in the AB in the register of the second number
45 ; 55
The content of the first address is transferred to the second register and printed, but not saved
24
Controlling transference, the next instruction is taken from the first address, in AB there is module of the result of the previous action
64
The same as in the operation 24, but the number isnt printed
74
Controlling transference, the next instruction is taken from the second address, in AB there is module of the result of the previous action
34
optional transference, the next instruction is taken from the second address if the result of the previous action had +, and according to the first address it had -
04
14
44
54
17
37
57
77
Operations Ostanova are different from each other by registers of AB and also selective and starting registers
.






References




1. V.V. Belinskij, V.M. Dolklar, B.M. Kagan, G.P. Lopato, N.Y. Matukhin A small electron computer M-3, M., issue The Scientific technical and producing experience, 1957

2. B.M. Kagan The history from the first hands, an interview to PC Week/Re, 46, December,9, 2003

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