Рогачев Юрий ВасильевичFour Generations of Small-sized computers named after M.A. Karzev (M – 4, M4 – 2M, M – 10, M – 13)
Научно-исследовательский институт вычислительных комплексов имени М.А. Карцева, научный консультант, firstname.lastname@example.org
Michail Karzev, a scientist in the field of computer engineering, doctor of technical sciences, professor, the chief designer of four computer generations and computer complexes for the work in real-time operation mode, founder and the first head of SRI of computer complexes came to this field as a student of radio engineering faculty of MEI. First notion about principles of digital computers building he got from I.S., Brook, a correspondent member of AS USSR in whose laboratory he took part in the creation of M -1 computer in 1950 projecting the main program sensor for it (a control unit). When creating N- 2 computer in 1952 1953 he was the head of engineers group and was a leader of the project.
The first generation of M-4 and M4-v computers
In 1957 a requirements specification of computer project for experimental complex of space controlling was developing in the Institute of electron mechanisms (this institute was founded on the base of laboratory after I.S. Brook).The specification was confirmed by A.L. Minz., a member of academy and I.S. Brook, a correspondent member of the academy. The head of the creation and putting into operation of the computer was M.A. Karzev. A special laboratory was organized №2. The new computer got the name of M-4. Special laboratory №2 was the base for staff creation and its growth up to a Scientific researching Institute of computer complexes and computer M-4 determined the direction of new M.A. Karzev's projects - a creation of computers series "M" for compute complexes that provides problem solving and information processing in real-time operation mode. M-4 opened the first generation of Karzev's computers of such class. The project staff: G.I. Tanetov, L.V. Ivanov, R.P. Shidlovskij, U.V. Rogachev, G. I. Smirnova, R.P. Makarova, E.S. Sherikhov, V.P. Kuznezov. The project and design papers for plant producer were finished in 1958.
M-4 had modern architecture for information processing in real-time operation mode and included: central processor (control unit, arithmetical unit, memory unit - operating memory and permanent memory of programs, constants, tables) and system of information input / output.
Arithmetical unit AU is semiconducting: trigger was built on transistors base P 16, logical schemes are on diodes D9. Impulse potential elements were used. Potential elements - diode logic, impulse-potential elements - two enter valve, the first one was impulse, the second one was potential. Trigger had impulse enters and potent ional exits. The base of AU were of one type cells every of witch had one class of processing apparatus. In the control unit of AU there were several triggers that formed chains and rings when doing this or that arithmetical operations with the help of diode logic. In this AU the first computer operation of square root calculation in the world was carried out.
Central controlling is for automatically controlling of operations fulfillment. It chooses from permanent memory of programs instructions and corresponding to the directions chooses necessary constants from permanent memory of constants and data that should be processed from operating memory, does some operations and records the results in necessary cells. According to program directions these results can be sent to code magnetic loggers of PR-16 type, to display device of information, to printing device. New data for processing came to operating memory directly from coupling device and input from perforated tape with the help of photo electrical reading device.
Operating memory is a ferrite device of matrix type for 1024 24-classes numbers. As a memory element core of 1,5 mm (interior - 1,1 mm) and the height of 0,7 mm diameter were used, they were made of magnetic material. The rotating cycle - 1,4 ms
Permanent memory of matrix type was built on the same cores. The difference is in order of information winding insertions.
Complex external devices included photo reading device from perforated tapes, "quick" printing device and special subscriber coupling for information input and output with parallel 14 -canals train. For information control electron indicators were used, for visual display of information and code loggers no perforated tape.
Computer m-4 was asynchronous, had one address system of commands, a great set of arithmetical operations including computer operation fulfillment (multiplying, double comparison, square rooting and others) and controlling operations. There was a principle of maximum loading of the whole hardware. For address transformation a special 10-class device was used. Reserves of productivity were used for automatically control of computer work by double checking of program parts and test-programs starting.
The main characteristics
Calculating system - binary
Number of double classes - 23
Number performing - with fixed comma
Average speed - 20 thousand operations per sec.(50 thousand operations of adding or subtracting per sec., 15 thousand operations of dividing or square rooting per sec.)
Volume of operating memory - 1024 23-classes of numbers
Volume of permanent memory - 1024 23-classes of numbers
Volume of permanent memory of constants - 128 12-classes of numbers
Volume of permanent memory of tables - 256 44-classes of numbers
Volume of buffer unit memory - 120 15-classes of numbers
Volume of buffer unit memory - 64 15-classes of numbers
Volume of buffer unit memory - 1280 32-classes of numbers
Input/output of information in real-time operation mode - parallel, 14-canals, speed 6250 numbers per sec
Information input speed from perforated tape - 45- 50 numbers per sec
Printing speed - 7 lines with hexadecimal figures per sec
Block-scheme computer M-4
CC - central controlling
AD - arithmetical device
OM - operating memory
MP - permanent memory of programs
MC - permanent memory of constants
MT - permanent memory of tables
BM - buffer memory of registers
IR -1, IR-2 - registers of information receiving
IG - registers of information giving
D-5 - information display device
PR-16 - magnetic loggers (magnetic tape)
BP-20 - printing device ("quick printing")
PRD - photo reading device
In 1960 there were built two sets of the computer. The first set was sent for docking with RFS of experimental complex. The second one was to control and information processing of RFS of other frequency range, so an additional device of initial processing with higher speed should be created and built for it. An absolutely new system of potentional logical elements with high frequency diffusive transistor using was carried out. The foundation for the system was inventor - a former of levels with multistep diode logical schemes. Functional scheme of the device had construction of large registers that provided simultaneous parallel processing up to 16 radio-location signals. These two new engineering ways provided the fulfillment of assigned requirements according to speed. The device included: a switch of sectors, transformer of codes, storage device, threshold device, recoding device, buffer memory. All hardware was placed in one box of computer M-4. The device of initial processing in 1961 was produced and decked with the second set of M-4 that got the name M4-M and switched to work with another one.
In July, 1962 the first set of computer M-4 in the experimental complex went through tests. Both sets worked together with radio location stations of experimental complex till 1966.
The second generation - computers M4-2M and M4-3M
In 1961-1062 there were researches in the field of computer creation with higher engineering characteristics of speed and reliability, more technological in production and convenient in using in the Karzev's laboratory along with M-4. at the beginning of 1963 when Karzev got the task for a new project element base, construction, most of structural and schemes questions had been carried out. The plant got the all papers and could start preparations for the production in the same year. According to requirements specification the computer was computer complexes of territory computer system construction that included several regional computer centers connected with transmission channels with the main computer center. All computer complexes got a task to provide permanent 24-hour non-stop work in real-time operation mode. New project got the name M4-2M. The project staff: the chief designer - Karzev M.A; L.V. Ivanov, U.V. Rogachev G.I., R.P. Shidlovskij, G.I Tanetov, V.A. Brik, L.Z. Liburkin, V.P. Kuznezov, E.S.Sherikhov, E.I. Zibul.
Computer M4-2M had one address system of commands with an ability to read constants as a second operand, a set of arithmetical operations with floating point, a group of logical operations and controlling operations. It had developed system od breaks, opportunity to work with double accuracy, high speed of reaction to external signals. Computer M4-2M is synchronous there is a conveyer of commands and operations and unusual class net - 29 classes was used. Arithmetical operations were fulfilled over operands with floating point: one class was signed, 8 classes defined the order and 20 classes made the mantissa of a number. So M4-2M had an enlarged range of numbers -from +127 to -128 and a diminished mantissa. System of commands had operations with getting the result of higher accuracy with 40-classes mantissa. In M4-2M any operation - arithmetical, logical, controlling or multiplying fulfilled for 4.5 ms, one computer stroke. This was provided with using one stroke of AD with "sum pyramid" for multiplying. There was one more new thing - conveyer.
Memory device of OM and PM were built on ferrite cores that were inserted in matrix with addressing and number windings. Later in the device of PM matrixes with inserted winding were changed into matrixes with electrical recording that made technology better and raise the memory volume. Blocks of OM are connected with controlling device by tires with 29-classes that formed number tire and command tire. So operands and commands can be read. It was convenient when tuning and debugging of users working programs.
Enter registers of arithmetical device had the connection with exit registers that gave an opportunity for arithmetical operations except taking operands out of memory and use the results of previous operations.
As a controlling computer M4-2M had a developed system of external breaks. There were 12 active and 12 passive breaks from controlling object. The time of computer reaction to active breaks was little: the changing into break program is about 2-3 computer strokes. It was an important advantage of the computer M4-2M.
Structural scheme of computer M4-2M
Tires of recording
Printing break signals
CD - Controlling device
AD -Arithmetical device (A, C, B, D - registers)
OM -Operating memory
PM - Permanent memory
ID - Input/output device
The main engineering characteristics
Calculating system - binary
Number of binary classes -29
Number presentation - with floating point
Speed - 220 thousand operations per sec
Modification memory volume 5e71 5e72 5e73
- operating memory Kb 30 60 120
- permanent memory Kb 60 120 120
When changing matrix of permanent memory with insertion into matrix with electrical recording of memory volume PM is enlarged in two times in every modification
Computer M4-2M (mod. 5E71)
The computer was produced in three modifications that were different in operating memory and permanent memory volumes (5E71, 5E72, 5E73). Such technical characteristics of the computer allowed using it computer complexes of different levels of the system. With this aim in addition to computer M4-2M systems of external devices and calculator were built on the same constructive and element base - computer M4-3M that provided an opportunity to send information of regional computer centers to the main computer center through connection channel.
External computer M4-3M worked parallel in the combination with M4-2M. It was a computer of parallel work that operated with 29-classes of binary numbers. Word command structure was according to principle for computer M4-2M. The system of external computer consisted of two devices: FD and CC. FD functioned in a classical way for controlling device of any computer: receiving and decoding of commands, address modification, creating of controlling signals and others. Controller of channels CC provided receiving and storage of queries from different devices of coupling, command receiving from central processor, organization of prior operating memory access and creating of controlling signals for coupling devices. Devices that were included into the external computer of operating memory had different chains of access thank to what it was possible to choose one number, information recording from coupling device, choosing numbers according to two addresses and other parallel operations connected with memory access. Arithmetical device AD had circular structure. Multiplying and dividing were fulfilled according to a "circle": multiplying - for 3 and dividing - for 5 strokes. A new algorithm of dividing was used - i.e. without remainders renewing for one cycle 4 bites of quotient were calculated, so the dividing was in hexadecimal system. The head of the project was U.N. Melnik and of the arithmetical device - V.A. Brik.
As it was said the plant began the preparations for computer producing in the middle of 1963. In 1964 the first series of these computers was produced and work of combining computers in computer complexes and there using started. From 1965 to 1969 17 computer complexes were built and put into operation including 5 complexes of computers with modification 5E72 for regional computer centers and main computer complex with modification 5E73, external computer M4-3M. In 1969 territory computer system that combined more than 50 computers was put into operation.
The production of computers M4-2M was up to 1986. It was produced about 200 such computers.
The third generation of computers M-10 and M-10M
In 1965 - 1967 in searching of new ways of higher computer productivity at present level of electronics and technology Karzev paid his attention to researching of multiprocessor architecture of computer systems. In his researches he showed four ways of parallel calculations and defined for every way possible hardware realization. That were the biggest problems for their solving it was needed high productivity of computers that had this pr that parallel types. That's why the most universal way of computer system building with maximum productivity was architecture of multiprocessor combined computer system. With such architecture in 1967 a project draft of computer complex CC M-9 with productivity up to 1 billion operations per sec. was worked out. This project wasn't realized completely but one ot ita parts - number unit became the foundation for third generation of computer M-10. A requirements specification of computer M-10 project was confirmed in November, 1969. It was a rather difficult task for designers. Having microschemes 217 with 15-25 ns speed for a valve and integration up to 3-5 valves in the frame and ferrite cores with external diameter 1 mm it was necessary to built a computer with speed of 5 mil operations per sec and memory with not less tham5 Mb. For the fulfillment of this task it was necessary 386 thousand microschemes, 353 thousand transistors and semiconductor diodes, 45.5 mil ferrite cores, 1.4 mil condensates and 1.4 mil strengths. Later Karzev wrote: "We can't say that project of computer M-10 was welcomed. We were said that we were crazy and that this computer wouldn't work. But we succeeded. We got state prize for this work:"
The project staff: the chief designer - M.A. Karzev; U.V. Rogachev, L.V. ivanov, L.Y Miller, A.A. Krupskij, R.P. Shidlovskij, V.A. Brik, E.I, Zibul, E.S. Sherikhov, L.Z. Liburkin, G.I. Smirniva, G.N. Pusenkov, L.D. Baranov.
The project began in 1970. In 1971 the plant got all design papers and started the production.
Computer M-10 - is a synchronized vector-parallel multiprocessor computer. It allows using practically all kinds of parallelism:
- synchronous program fulfillment with different processors with information exchange through the system of synchronous exchange (program rate of "score")
- synchronous fulfillment of operation set in one command (architecture of "broad command")
- operation fulfillment over data vectors
- conveyer of commands and operations
The computer had number of processors that were two independent arithmetical devices that synchronous fulfilled different arithmetical and logical operations. Every device consisted of one, two, four or eight processors that were accordingly into 128, 64, 32 or 16-classed
The second kind of processors is that worked synchronous - controlling device.
A functional bar of the controlling device was realized with the help of 16-classes registers that were called sign registers. Simultaneously with the work of theses processors in the controlling device one more set of operations with fixed point over content of address modifier is fulfilled. There are 16 modifier in M-10. Each one had 22 classes that corresponds to memory address of M-10
The third kind of processors M-10 are two working connection channels PROCESSOR - MEMORY that are to read operands in memory through enter registers of arithmetical processors and record the results of operations into memory. The maximum memory access through one channel is 512 b that allows filling enter registers of all arithmetical processors for one cycle. Memory of the computer has three kinds: main operating memory with 512 Kb volume (ferrite), permanent memory with 512 Kb volume (condenser type on perforated tapes) and big operating memory with 4 Mb volume (ferrite). The speed of two way exchange between main and big memories is 20 Mb per sec to each way parallel with calculating in the central processor. The main feature of the computer is wide and exchange format of memory access: for one access form 2 to 64 b can be taken. Interpretation and commutation of the information receiving from OM and PM to necessary format are fulfilled in commutating coding device (CD).
The fourth kind of processors is a multiplexer channel of direct memory access that allows carrying out input/output through duplex channels with total speed up to 7 Mb per sec. Every channel can be connected with up to 6 one-type devices.
The next parallel processors are special schemes of hardware accuracy control of computer and user program control. Interconnection of these processors is carried out through cascading system of program breaks that is a part of central controlling device. It can also receive external signals (up to 32).
There chains in computer that allow combining up to 7 computers M-10 into one synchronous complex that works form stroke generator. At each stroke computer working in complex can give an array of data of 64 b and receive an array of 64 b from any computer.
CD - Controlling device
AD - Arithmetical device
OM - Main operating memory
BM - Big memory (the second level of operating memory)
PM - Permanent memory
CD - Commutating coding device
CC - Channel controller (multiplex channel)
CD - Subscriber coupling device
Average speed - 5.1 mil operations per sec
Total volume of memory - 5 Mb
Buffer memory volume of multiplexer channel 64 Kb
Break program system 72-channel with 5 levels of prior
Simultaneous work is provided in the mode of time dividing of 8 users at 8
Operations with fixed and floating point are carried out simultaneously atone stroke
There can be vector operations, e.g. at one stroke calculating of scale product of vectors can be done
All hardware of the computer M-10 was placed in 31 standard boxes, hardware took 21 boxes of memory devices. By 1974 there were produced three sets of computers for computer complex. At the same time these computers were debugging of software and users programs of the complex. In 1976 computer and computer complex passed successfully state testing. Computer complex was put into operation in the mode of non-stop 24-hours work. The production of the computers was continued. At this time new memory devices were created with using big integral schemes that 2.5 times reduce the number of boxes. The computer with new devices got the name M-10M and from 1977 computer with new integration was produced. Computers M-10 and M-10M were programming compatible and interchangeable. A whole number of unique computer complexes including computer complexes with six computers were made on their base. Some computer complexes work nowadays. The production of these computers was till 1992 and there produced about 50 sets. Mathematical supplying of M-10 includes:
- operating system that provides time and hardware division, dialogue mode of simultaneous debugging up to 8 independent programs and multiprogramming mode of automatically 8 independent problems passing;
- system of programming that includes computer oriented language, problem oriented language and corresponding translators and means of debugging;
- library of routine and standard programs
- control program of functioning
While broadening of computer using among users the set of mathematical supplying was changing.
Valuing the contribution of computer M-10 architecture into the computer development in the USSR B.A. Golovkin, professor, wrote:
": M.A. Karzev offered the firs in the world conception of complete parallel computer system with paralleling on all four levels (programs, commands, data and words) and it is very important. This conception was realized on the base of computer M-10 complexes.
Parallel architecture contribution into the productivity raising was so good that at long length of computer stroke at 1.9 ms the productivity of M-10 was 5.1 mil operations per second at testing. Computer M-10 was the most powerful computer before "Elbrus" computer.
So, according to architecture principles, conception and realization M-10 defined a new class of computers and was the first one in the country of vector parallel computer realization:."
The fourth generation of M.A. Karzev's computers - M-13
At the end of 1977 it was clear that the idea of multiprocessor computers were reality and M-10 proved its potential. Working at computer project of new generation M.A. Karzev based on the experience of M-10 and complexes building. This experience showed that structure of new computer must be more flexible according to productivity and interconnecting. This task was for the project staff when starting the project of computer M-13.
Project of computer M-13 must have three bases of the model and a number od modifications with different arithmetical devices, memory devices and additional external devices. All models were built according to module principle using the same control spectrum. Changing of small model into a medium one was carried out with modules number rising.
Program compatibility of systems of M-13 was achieved with one language for all models of computer and one mathematical supply that had mode in real-time operation mode, dialogue mode of time division and display providing for creation, broadcasting and debugging of programs in computer oriented, problem oriented and universal languages.
In the part of element, constructive and engineering bases the most progressive engineering ways were used. In logical units microschemes of 133, 130, 530 series were used. For memory devices microschemes of semiconductor memory of wide usage were used.
Requirements specification for computer M-13 project and computer complex on its base was confirmed in 1980. The chief designer was M.A. Karzev; project staff: U.B Rogachev, L.Y. Miller, A.U. Karasik, L.V. Ivanov, R.P. Shidlovskij, A.A. Krupskij, and E.I. Zibul. The project creation was finished in 1982.
M-13 is a multiprocessor, vector-conveyer computer with conveyorization at data level. There is a vector arithmetical device with parallel reconfigurable conveyer devices of processing. Every device carries out the same operation at conveyer mode but with different operands. M-13 consists of central processing part; hardware of system operation support, subsystem of input/output and specializing processor part.
Central processing part, for basic calculations, has arithmetical controlling device (ACD), memory device (MD), central controlling device (CCD) and editing device (ED).
ACD - is a vector conveyer arithmetical logical device. It is divided in 16, 8 or 4 arithmetical processor depending on the operand format (8, 16, 32 classes). Computer M-13 could have 1, 2 or 4 ACD that make one conveyer device. All arithmetical processors work synchronous carrying out this or that operation with all pairs of operands. Every arithmetical operand is conveyer device. ACD worked with numbers as with fixed as floating point.
CCD is a central controlling device that includes Boolean processor for commands controlling and maximization in vector processing and address modification processor with productivity of 3 mil operations per sec to control address space.
ED - central editing device provides carrying out a number of special procedures connected with interconnection of linear of processors and blocks of memory. They are: massif compacting under the mask with the aim of gaps excluding that appear in the process of parallel processing; circular shift of a line of information; transposition of information line. Besides procedures connected with organization of computer conveyer are realized in the device: three-address register memory access (2 readings + 1 recording simultaneously) for serving speeding of ACD and formats co-ordination of processing in different integrations of M-13 with saving their program compatibility.
Hardware of system operation support includes central controlling processor CCP and address wire controlling device (WCD).
CCP - central controlling processor provides hardware support of operation system and virtual memory and processors controlling. It is connected with controlling interfaces with all computer processors.
WCD - address wire controlling device includes tables of virtual mathematical memory. It connects all devices of the computer and memory with large-format wires.
Subsystem of input/output includes multiplexer channel (MC) and subscriber coupling device (SCD)
MC - multiplexer channel is for coupling of subsystem input/output with central controlling processor and memory. It realizes the starting of changing operations on channels, production control of channels work, organization of virtual and relative addressing and breaks processing from channels. MC carries out multiplexing of data exchange between subscriber coupling device and memory and carries out the transformation of formats.
SCD - subscriber coupling device has coupling processors that allow connecting with standard as particularized devices that are included into controlling objects. Depending on the configuration SCD can have from 4 up to `128 coupling processors with programming subscriber interface that provided problem solving about computer coupling with different and unique interfaces of subscribers in real time.
Particularized processor part has processors of coherent processing PCP, technical controlling TC and memory of hypotheses device MHD.
PCP is a processor of coherent processing and particularized vector-conveyer calculator. Program controlling conveyer architecture device of two-point transformation is used there. The base for it is a unit for base operation fulfillment of Fourier's quick transformation. The appliance of this base operation allowed fulfillment of many operations that are needed in signal digital processing of algorithms on the same hardware: calculating of maximum value in massive, comparing of massive with threshold value, calculating of sum product of missives, calculating of correlating matrixes and others. PCP does multiplying of two complex numbers. There are four processors in the box. The equivalent productivity of one box is 120 mil operations per sec. The configuration of boxes number can be from one up to twenty.
TC technical controlling is to couple particularized and central processing parts and for production control of different groups of PCP. The information path of exchanging between central processor and memory is realized with the help reading and recording wires using. TC fulfills in the multiplexing mode the data exchange according to vertical interface between separate groups of PCP in the central processing part. There is a co-ordination of formats and transformation of number representing from particularized processor part format into central processing part.
MHD, a memory of hypotheses device, is a particularized multiport storage.
It is used in CPP for long storage of "system" information of PCP and for "temporal" storage of information.
Performance attributes of M-13
Central processing part
- speed op/sec 12ml, 24ml, 48ml
- memory volume, Mb 8.5, 17, 34
- aggregate throughput
of central switchboard Mb/s 800, 1600, 3200
-Of multiplexer channel Mb/s 40, 70, 100
- Number of coupling processors 8, 16, 128
- Maximum speed op/s 350 ml
Particularized processor part
- controlling hypotheses memory volume Mb 4 8 128
- maximum equivalent speed op/s 2.4 bl
- on changeable magnet disks Mb 200
- on magnet tape 42
The series production of computer M-13 began in 1984 with a delay for two years after Karzve's death. The author of this article managed to start the beginning of computer M-13 production at Zagorsk electromechanical plant in 1984. In 1986 the plant produced the first two computers and the further production was according to the plan. In 1991 a computer complex of 6 computers passed through state testing successfully and was put into operation in non-stop 24-hour work.
Computer at testing showed the following data:
- productivity of CPP 24 ml op/s
- memory volume of CPP 17 Mb
- productivity of PPP 1.2 bl op/s
- memory volume 40 Mb
The computer production was till 1992. 18 sets of computer complexes were produced.